1. Field of the Invention
The present invention relates to semiconductor memory devices each including memory cells arranged in an array of columns and rows and capable of performing write and read operations at random.
2. Description of the Prior Art
As conventional semiconductor memory devices, semiconductor memory devices in each of which data read out immediately after power-on is initialized to a predetermined value, e.g., a device disclosed in Japanese Unexamined Patent Publication (Kokai) No. 01-113995, are known.
FIG. 1 is a circuit diagram showing a memory cell (an SRAM memory cell) of the conventional semiconductor memory device disclosed in the above publication. This semiconductor memory device includes a memory cell array in which memory cells 101 are arranged in rows and columns. Each of the memory cells 101 includes: inverters 101a and 101b; and access transistors Ta1 and Ta2. Each of the inverters 101a and 101b is provided between a power-supply terminal and a ground terminal and configured by connecting a p-channel field effect transistor (p-FET) Tp and an n-channel field effect transistor (n-FET) Tn in series via an internal node 101c or 101d. The access transistor Ta1 or Ta2 is connected between the internal node 101c or 101d in the inverter 101a or 101b, respectively, and one of a pair of bit lines BIT and NBIT, respectively. The gates of the access transistors Ta1 and Ta2 are connected to a word line WL. A state in which one of the internal nodes 101c and 101d has a high potential and the other has a low potential corresponds to data “1” and the opposite state corresponds to data “0”. Under these conditions, an input/output circuit is configured to write and read data in/from some of the memory cells 101 selected by the word line WL via the bit lines BIT and NBIT.
In the semiconductor memory device shown in FIG. 1, the gate length or the gate width of each FET in the inverter 101a in each of the memory cells 101 differs from the gate length or the gate width of each FET in the other inverter 101b. This configuration causes a difference in current driving ability between the inverters 101a and 101b, so that potentials of the internal nodes 101c and 101d in the memory cells 101 differ from each other when power is turned on. Accordingly, initialization is performed such that the memory cell 101 stores data “0” or “1”.
However, the conventional semiconductor memory devices have the following drawbacks.
In the conventional semiconductor memory device shown in FIG. 1, the two inverters 101a and 101b in the memory cell have different gate lengths or gate widths as described above. With such a configuration, initialization is performed to obtain only one state in which data “0” or “1” is stored. In addition, since the inverters 101a and 101b have different current driving abilities, the speed at reading initialized data is different from the speed at reading data having an inverted logical value of the initialized data. Moreover, the structure in which the gate sizes of the FETs in the respective inverters are not balanced causes another drawback in which the data holding characteristic (noise immunity) of memory cells and the speed of reading from the memory cells are readily affected by variations in fabrication.